The semiconductor sector is seeing a new wave of expansion. While there has never been a greater demand for chip innovation, Moore’s Law 2D scaling is stalling. With each successive iteration, chip shrinking takes longer and costs more. As chipmakers and systems strive to continue driving advancements in power, performance, area, cost, and speed to market, new design and production paradigms are required.
The next revolution in advanced packaging provides a major improvement over conventional multi–chip packaging techniques, with the substrate’s wiring used to complete the electrical interconnections between chips. Each successive technology offers higher I/O density, as well as lower power consumption per bit of data transfer. Nirmalya Maity, corporate vice president of Advanced Packaging at Applied Materials, writes in this special project how to accelerate the trend through advanced packaging techniques.
Applied Novel Devices (AND), a provider of new semiconductor device architectures applicable to discrete and integrated power devices, has introduced a major industry breakthrough with its new class of silicon power MOSFET (ANDFET) technology, which features a sub–30–µm substrate that offers significant benefits for fast–switching and power–conversion applications.
Meanwhile, silicon photonics is evolving from a technology reserved for niche markets, such as high–performance computing or military applications, to an accessible technology for higher–volume markets, including the consumer one. Designed to address growing bandwidth demands and high–level applications that rely on artificial intelligence and machine learning, the next silicon photonics platforms are ready for the market.
The modular architecture of photonic chips simplifies the design, fabrication, and integration of quantum and other optoelectronic solutions. The forthcoming architectures’ modularity, speed, and room–temperature operation will enable photonics to contribute to the rapid construction of quantum computers.
Here’s an excerpt from Ed Seng, strategic marketing manager for Advanced Digital at Teradyne, in which he examines a post–Moore’s Law world:
“Even in a post–Moore’s law world, semiconductor technology continues to advance, seeking to yield improvements and pivoting into new technical directions, such as the advanced packaging of multiple heterogenous integrated semiconductor dies, or chiplets. The result is new manufacturing processes that add complexity and defectivity — making test a key component for success.
Advanced packaging continues the benefits of Moore’s Law in ways other than just scaling fab process nodes. Disaggregating functions, the opposite of the monolithic SoC approach, allows for focusing advanced fab process design on just the core compute and accelerators, thus saving design effort and cost by not changing other functions.
The present-day focus is “optimization per use case” enabled by the flexibility to more easily choose functions to include in the packaged device. The result continues to deliver the performance and power wins previously seen with Moore’s Law.”
Articles in this Special Project:
As Classic Moore’s Law Dims, Heterogeneous Integration Steps Into the Limelight
Moore’s Law 2D scaling is slowing, prompting the need for heterogeneous integration and advanced packaging techniques such as hybrid bonding.
A Post-Moore’s Law World
In a post–Moore’s Law world there will be lots of unknowns. Will the benefits of chiplets be realized? How will new die interface standards evolve? Test program and result data sharing are key to making this work.
Marvell targets cloud data centers with silicon photonics platform
Marvell Technology’s latest cloud–optimized silicon photonics platform aims to address growing bandwidth demands while also providing lower costs and better power.
New Silicon Power MOSFET Technology Rivals GaN with Near-Zero Reverse Recovery and Low On-Resistance
By: Maurizio Di Paolo Emilio
This new silicon power MOSFET offers near–zero reverse–recovery losses, bringing an advantage to silicon that is usually seen only in gallium nitride technologies while maintaining the cost and compatibility advantages of silicon.
Photonic Chips for Fault-Tolerance Quantum Computing
By: Maurizio Di Paolo Emilio
The collaboration between Xanadu and Imec involves fabricating low-loss silicon nitride circuits that can correct qubit errors and increase capacity.
Silicon Photonics Sticks Its Head Above the Parapet
By: Eric Mounier and Alexis Debray
It took almost 20 years for silicon photonics to evolve from a technology reserved for niche markets, such as high–performance computing or military applications, to an accessible technology for higher-volume markets, including consumer.
Further reading from around the web:
The promise of silicon photonics
Thirty Years in Silicon Photonics: A Personal View
Silicon Photonics May Remedy the Interconnect Bottlenecks of Moore’s Law
Integrated photonics will save Moore’s Law
Photonic Computers give Moore’s Law a new lease on life
Perspective on the future of silicon photonics and electronics
Intel sees bright future for silicon photonics, moving information at light speed in datacenters and beyond
For next breakthrough transistor technology I propose the vacuum channel transistor. In US9,331,189 patent from the UNIVERSITY OF PITTSBURGH the vacuum channel transistor can realize lower voltage operation like 2V for the gap between the Source and the Drain less than the mean-free path of electrons in air. In this case electrons can travel through air under room temperature without scattering. And electron field emission is based on the Fowler Nordheim tunneling effect, but the Coulombic repulsion among electrons in accumulation or inversion layer is expected to lower the energy barrier at the cleaved edge ( See Mytmgji Kim eta.1., Ultraviolet-enhanced photodetection in a graphene/SiO2/Si capacitor structure with a vacuum channel; Citation: Journal of Applied Physics 118). I proposed higher performance vacuum channel transitor than this patent, and also showed optical data transmishon circuit for LSI and stacked PCB layers without via using this vacuum channel transistor. For more information, please visit yoshiyuki ando@linkedin.
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